*Instruction Pairing Summary
*
*The following abbreviations are used in the Pairing column of the integer table in this Appendix:
*NP       Not pairable, executes in U pipe
*PU       Pairable if issued to U pipe
*PV       Pairable if issued to V pipe
*UV       Pairable in either pipe
*
*
*In the floating-point table in this Appendix:
*FX       Pairs with FXCH
*NP       No pairing.
*
*The I/O instructions are not pairable. 
*
*Integer Instruction Pairing
*
*INSTRUCTION     FORMAT  Pairing 
AAA  ASCII Adjust after Addition       NP      
AAD  ASCII Adjust AX before Division   NP      
AAM  ASCII Adjust AX after Multiply    NP      
AAS  ASCII Adjust AL after Subtraction NP      
ADC  ADD with Carry    PU      
ADD  Add       UV      
AND  Logical AND       UV      
ARPL  Adjust RPL Field of Selector     NP      
BOUND  Check Array Against Bounds      NP      
BSF  Bit Scan Forward  NP      
BSR  Bit Scan Reverse  NP      
BSWAP  Byte Swap       NP      
BT  Bit Test   NP      
BTC  Bit Test and Complement   NP      
BTR  Bit Test and Reset        NP      
BTS  Bit Test and Set  NP      
CALL  Call Procedure (in same segment)         
   direct       1110 1000 : full displacement   PV      
   register indirect    1111 1111 : 11 010 reg  NP      
   memory indirect      1111 1111 : mod 010 r/m NP      
CALL  Call Procedure (in other segment)        NP      
CBW  Convert Byte to Word CWDE  Convert Word to Doubleword   NP      
CLC  Clear Carry Flag  NP      
CLD  Clear Direction Flag      NP      
CLI  Clear Interrupt Flag      NP      
CLTS  Clear Task-Switched Flag in CR0  NP      
CMC  Complement Carry Flag     NP      
CMP  Compare Two Operands      UV      
CMPS   NP
CMPSB  NP
CMPSW  NP
CMPSD  Compare String Operands        NP      
CMPXCHG  Compare and Exchange  NP      
CMPXCHG8B  Compare and Exchange 8 Bytes        NP      
CWD  Convert Word to Dword CDQ  Convert Dword to Qword       NP      
DAA  Decimal Adjust AL after Addition  NP      
DAS  Decimal Adjust AL after Subtraction       NP      
DEC  Decrement by 1    UV      
DIV  Unsigned Divide   NP      
ENTER  Make Stack Frame for Procedure Parameters       NP      
HLT  Halt              
IDIV  Signed Divide    NP      
IMUL  Signed Multiply  NP      
INC  Increment by 1    UV      
IN    I/O NP
INS    "  NP
INSB   "  NP
INSW   "  NP
INSD   "  NP
INT n  Interrupt Type n        NP      
INT  Single-Step Interrupt 3   NP      
INTO  Interrupt 4 on Overflow  NP      
INVD  Invalidate Cache NP      
INVLPG  Invalidate TLB Entry   NP      
IRET   NP
IRETD  Interrupt Return   NP      
* The next line needs altering...
JA       Jump on above            PV
JAE      Jump above equal         PV
JB       Jump on below            PV
JBE      Jump below equal         PV
JC       Jump on carry            PV
JE       Jump on equal            PV
JG       Jump on greater          PV
JGE      Jump greater equal       PV
JL       Jump on less             PV
JLE      Jump less equal          PV
JMP      Jump unconditional       PV
JNA      Jump not above           PV
JNAE     Jump not above equal     PV
JNB      Jump not below           PV
JNBE     Jump not below equal     PV
JNC      Jump not carry           PV
JNE      Jump not equal           PV
JNG      Jump not greater         PV
JNGE     Jump not greater equ     PV
JNL      Jump not less            PV
JNLE     Jump not less equal      PV
JNO      Jump not overflow        PV
JNP      Jump not parity          PV
JNS      Jump not sign            PV
JNZ      Jump not zero            PV
JO       Jump overflow            PV
JP       Jump parity              PV
JPE      Jump parity even         PV
JPO      Jump parity odd          PV
JS       Jump on sign             PV
JZ       Jump on zero             PV
JCXZ   NP
JECXZ  Jump on CX/ECX Zero        NP      
JMP  Unconditional Jump (to same segment)              
   short        1110 1011 : 8-bit displacement  PV      
   direct       1110 1001 : full displacement   PV      
   register indirect    1111 1111 : 11 100 reg  NP      
   memory indirect      1111 1111 : mod 100 r/m NP      
JMP  Unconditional Jump (to other segment)     NP      
LAHF  Load Flags into AH Register      NP      
LAR  Load Access Rights Byte   NP      
LDS  Load Pointer to DS        NP      
LEA  Load Effective Address    UV      
LEAVE  High Level Procedure Exit       NP      
LES  Load Pointer to ES        NP      
LFS  Load Pointer to FS        NP      
LGDT  Load Global Descriptor Table Register    NP      
LGS  Load Pointer to GS        NP      
LIDT  Load Interrupt Descriptor Table Register NP      
LLDT  Load Local Descriptor Table Register     NP      
LMSW  Load Machine Status Word NP      
LOCK  Assert LOCK# Signal Prefix               
LODS  NP
LODSB  NP
LODSW  NP
LODSD  Load String Operand    NP      
LOOP  Loop Count       NP      
LOOPZ  NP
LOOPE  Loop Count while Zero/Equal       NP      
LOOPNZ  NP
LOOPNE  Loop Count while not Zero/Equal NP      
LSL  Load Segment Limit        NP      
LSS  Load Pointer to SS        0000 1111 : 1011 0010 : mod reg r/m     NP      
LTR  Load Task Register        NP      
MOV  Move Data UV      
MOV  Move to/from Control Registers    NP      
MOV  Move to/from Debug Registers      NP      
MOV  Move to/from Segment Registers    NP      
MOVS    NP
MOVSB   NP
MOVSW   NP
MOVSD  Move Data from String to String        NP      
MOVSX  Move with Sign-Extend   NP      
MOVZX  Move with Zero-Extend   NP      
MUL  Unsigned Multiplication of AL, AX or EAX  NP      
NEG  Two's Complement Negation NP      
NOP  No Operation      1001 0000       UV      
NOT  One's Complement Negation NP      
OR  Logical Inclusive OR       UV      
OUT       NP
OUTS      NP
OUTSB     NP
OUTSW     NP
OUTSD     NP
POP  Pop a Word from the Stack         
   reg  1000 1111 : 11 000 reg  UV      
      or        0101 1 reg      UV      
   memory       1000 1111 : mod 000 r/m NP      
POP  Pop a Segment Register from the Stack     NP      
POPA  NP
POPAD  Pop All General Registers  NP      
POPF  NP
POPFD  Pop Stack into FLAGS or EFLAGS Register    NP      
PUSH  Push Operand onto the Stack              
   reg  1111 1111 : 11 110 reg  UV      
      or        0101 0 reg      UV      
   memory       1111 1111 : mod 110 r/m NP      
   immediate    0110 10s0 : immediate data      UV      
PUSH  Push Segment Register onto the Stack     NP      
PUSHA  NP
PUSHAD  Push All General Registers       NP      
PUSHF NP
PUSHFD  Push Flags Register onto the Stack       NP      
RCL  Rotate thru Carry Left            
   reg by 1     1101 000w : 11 010 reg  PU      
   memory by 1  1101 000w : mod 010 r/m PU      
   reg by CL    1101 001w : 11 010 reg  NP      
   memory by CL 1101 001w : mod 010 r/m NP      
   reg by immediate count       1100 000w : 11 010 reg : imm8 data      PU      
   memory by immediate count    1100 000w : mod 010 r/m : imm8 data     PU      
RCR  Rotate thru Carry Right           
   reg by 1     1101 000w : 11 011 reg  PU      
   memory by 1  1101 000w : mod 011 r/m PU      
   reg by CL    1101 001w : 11 011 reg  NP      
   memory by CL 1101 001w : mod 011 r/m NP      
   reg by immediate count       1100 000w : 11 011 reg : imm8 data      PU      
   memory by immediate count    1100 000w : mod 011 r/m : imm8 data     PU      
RDMSR  Read from Model-Specific Register       NP      
REP LODS  Load String  NP      
REP MOVS  Move String  NP      
REP STOS  Store String NP      
REPE CMPS  Compare String (Find Non-Match)     NP      
REPE SCAS  Scan String (Find Non-AL/AX/EAX)    NP      
REPNE CMPS  Compare String (Find Match)        NP      
REPNE SCAS  Scan String (Find AL/AX/EAX)       NP      
RET  Return from Procedure (to same segment)   NP      
RET  Return from Procedure (to other segment)  NP      
ROL  Rotate (not thru Carry) Left              
   reg by 1     1101 000w : 11 000 reg  PU      
   memory by 1  1101 000w : mod 000 r/m PU      
   reg by CL    1101 001w : 11 000 reg  NP      
   memory by CL 1101 001w : mod 000 r/m NP      
   reg by immediate count       1100 000w : 11 000 reg : imm8 data      PU      
   memory by immediate count    1100 000w : mod 000 r/m : imm8 data     PU      
ROR  Rotate (not thru Carry) Right             
   reg by 1     1101 000w : 11 001 reg  PU      
   memory by 1  1101 000w : mod 001 r/m PU      
   reg by CL    1101 001w : 11 001 reg  NP      
   memory by CL 1101 001w : mod 001 r/m NP      
   reg by immediate count       1100 000w : 11 001 reg : imm8 data      PU      
   memory by immediate count    1100 000w : mod 001 r/m : imm8 data     PU      
RSM  Resume from System  Management Mode       NP      
SAHF  Store AH into Flags      NP      
SAL  Shift Arithmetic Left     same instruction as SHL         
SAR  Shift Arithmetic Right            
   reg by 1     1101 000w : 11 111 reg  PU      
   memory by 1  1101 000w : mod 111 r/m PU      
   reg by CL    1101 001w : 11 111 reg  NP      
   memory by CL 1101 001w : mod 111 r/m NP      
   reg by immediate count       1100 000w : 11 111 reg : imm8 data      PU      
   memory by immediate count    1100 000w : mod 111 r/m : imm8 data     PU      
SBB  Integer Subtraction with Borrow   PU      
SCAS    NP
SCASB   NP
SCASW   NP
SCASD  Scan String    NP      
*The next line needs altering...
SET   Byte Set on Condition   NP      
SGDT  Store Global Descriptor Table Register   NP      
SHL  Shift Left                
   reg by 1     1101 000w : 11 100 reg  PU      
   memory by 1  1101 000w : mod 100 r/m PU      
   reg by CL    1101 001w : 11 100 reg  NP      
   memory by CL 1101 001w : mod 100 r/m NP      
   reg by immediate count       1100 000w : 11 100 reg : imm8 data      PU      
   memory by immediate count    1100 000w : mod 100 r/m : imm8 data     PU      
SHLD  Double Precision Shift Left              
   register by immediate count  0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8     NP      
   memory by immediate count    0000 1111 : 1010 0100 : mod reg r/m : imm8      NP      
   register by CL       0000 1111 : 1010 0101 : 11 reg2 reg1    NP      
   memory by CL 0000 1111 : 1010 0101 : mod reg r/m     NP      
SHR  Shift Right               
   reg by 1     1101 000w : 11 101 reg  PU      
   memory by 1  1101 000w : mod 101 r/m PU      
   reg by CL    1101 001w : 11 101 reg  NP      
   memory by CL 1101 001w : mod 101 r/m NP      
   reg by immediate count       1100 000w : 11 101 reg : imm8 data      PU      
   memory by immediate count    1100 000w : mod 101 r/m : imm8 data     PU      
SHRD  Double Precision Shift Right             
   register by immediate count  0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8     NP      
   memory by immediate count    0000 1111 : 1010 1100 : mod reg r/m : imm8      NP      
   register by CL       0000 1111 : 1010 1101 : 11 reg2 reg1    NP      
   memory by CL 0000 1111 : 1010 1101 : mod reg r/m     NP      
SIDT  Store Interrupt Descriptor Table Register        NP      
SLDT  Store Local Descriptor Table Register    NP      
SMSW  Store Machine Status Word        NP      
STC  Set Carry Flag    NP      
STD  Set Direction Flag        NP      
STI  Set Interrupt Flag                
STOS   NP
STOSB  NP
STOSW  NP
STOSD  Store String Data      NP      
STR  Store Task Register       NP      
SUB  Integer Subtraction       UV      
TEST  Logical Compare          
   reg1 and reg2        1000 010w : 11 reg1 reg2        UV      
   memory and register  1000 010w : mod reg r/m UV      
   immediate and register       1111 011w : 11 000 reg : immediate data NP      
   immediate and accumulator    1010 100w : immediate data      UV      
   immediate and memory 1111 011w : mod 000 r/m : immediate data        NP      
VERR  Verify a Segment for Reading     NP      
VERW  Verify a Segment for Writing     NP      
WAIT  Wait     1001 1011       NP      
WBINVD  Write-Back and Invalidate Data Cache   NP      
WRMSR  Write to Model-Specific Register        NP      
XADD  Exchange and Add NP      
XCHG  Exchange Register/Memory with Register   NP      
XLAT  NP
XLATB  Table Look-up Translation  NP      
XOR  Logical Exclusive OR      UV      
*
*Floating-Point Instruction Pairing
*INSTRUCTION     FORMAT  Pairing 
*
F2XM1  Compute 2ST(0)  1      NP      
FABS  Absolute Value   FX      
FADD  Add      FX      
FADDP  Add and Pop     FX      
FBLD  Load Binary Coded Decimal        NP      
FBSTP  Store Binary Coded Decimal and Pop      NP      
FCHS  Change Sign      FX      
FCLEX  Clear Exceptions        NP      
FCOM  Compare Real     FX      
FCOMP  Compare Real and Pop    FX      
FCOMPP  Compare Real and Pop Twice             
FCOS  Cosine of ST(0)  NP      
FDECSTP  Decrement Stack-Top Pointer   NP      
FDIV  Divide   FX      
FDIVP  Divide and Pop  FX      
FDIVR  Reverse Divide  FX      
FDIVRP  Reverse Divide and Pop FX      
FFREE  Free ST(i) Register     NP      
FIADD  Add Integer     NP      
FICOM  Compare Integer NP      
FICOMP  Compare Integer and Pop        NP      
FIDIV   NP      
FIDIVR  NP      
FILD  Load Integer     NP      
FIMUL   NP      
FINCSTP  Increment Stack Pointer       NP      
FINIT  Initialize Floating-Point Unit  NP      
FIST  Store Integer    NP      
FISTP  Store Integer and Pop   NP      
FISUB   NP      
FISUBR  NP      
FLD  Load Real         
   32-bit memory        11011 001 : mod 000 r/m FX      
   64-bit memory        11011 101 : mod 000 r/m FX      
   80-bit memory        11011 011 : mod 101 r/m NP      
   ST(i)        11011 001 : 11 000 ST(i)        FX      
FLD1  Load +1.0 into ST(0)     NP      
FLDCW  Load Control Word       NP      
FLDENV  Load FPU Environment   NP      
FLDL2E  Load log2() into ST(0) NP      
FLDL2T  Load log2(10) into ST(0)       NP      
FLDLG2  Load log10(2) into ST(0)       NP      
FLDLN2  Load log(2) into ST(0) NP      
FLDPI  Load  into ST(0)        NP      
FLDZ  Load +0.0 into ST(0)     NP      
FMUL  Multiply FX      
FMULP  Multiply        FX      
FNOP  No Operation     NP      
FPATAN  Partial Arctangent     NP      
FPREM  Partial Remainder       NP      
FPREM1  Partial Remainder (IEEE)       NP      
FPTAN  Partial Tangent NP      
FRNDINT  Round to Integer              
FRSTOR  Restore FPU State      NP      
FSAVE  Store FPU State NP      
FSCALE  Scale  NP      
FSIN  Sine     NP      
FSINCOS  Sine and Cosine       NP      
FSQRT  Square Root     NP      
FST  Store Real        NP      
FSTCW  Store Control Word      NP      
FSTENV  Store FPU Environment  NP      
FSTP  Store Real and Pop       NP      
FSTSW  Store Status Word into AX       NP      
FSTSW  Store Status Word into Memory   NP      
FSUB  Subtract FX      
FSUBP  Subtract and Pop        FX      
FSUBR  Reverse Subtract        FX      
FSUBRP  Reverse Subtract and Pop       FX      
FTST  Test     FX      
FUCOM  Unordered Compare Real) FX      
FUCOMP  Unordered Compare and Pop      FX      
FUCOMPP  Unordered Compare  and Pop Twice      FX      
FXAM  Examine  NP      
FXCH  Exchange ST(0) and ST(i) EX        
FXTRACT  Extract Exponent  and Significand     NP      
FYL2X  ST(1)  log2(ST(0))      NP      
FYL2XP1  ST(1)  log2(ST(0) + 1.0)      NP      
FWAIT  Wait until FPU Ready            
